* LSTTL input logic compatible
  – VIL(max) = 0.8 V, VIH(min) = 2 V
* CMOS input logic compatible
  – II ≤ 1 µA at VOL, VOH
* Buff.

* Alarm / tamper detect circuit
* S-R latch 3 Description This device contains three independent 3-input NAND .

This device contains three independent 3-input NAND gates. Each gate performs the Boolean function Y = A
* B
* C in positive logic. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) CD74HCT10M SOIC (14) 8.70 mm × 3.90 mm CD74.

CD54HCT109

CD54HCT10F

CD54HCT11

CD54HCT112

CD54HCT123

CD54HCT125

CD54HCT126

CD54HCT132

CD54HCT132J

CD54HCT138

CD54HCT138F

CD54HCT139

CD54HCT14